Summary: Processors are theactual working part of a computer, performing arithemetic, logic, and otheroperations needed to run computer programs.
- processors
- CISC
- RISC
- DSP
- Hybrid
A computer is a programmablemachine. There are two basic kinds of computers: analog and digital.
Analog computers are analog devices.That is, they have continuous states rather than discrete numbered states. Ananalog computer can represent fractional or irrational values exactly, with noround-off. Analog computers are almost never used outside of experimentalsettings.
A digital computer is aprogrammable clocked sequential state machine. A digital computer uses discretestates. A binary digital computer uses two discrete states, such aspositive/negative, high/low, on/off, used to represent the binary digits zeroand one.
The classic crude oversimplication of acomputer is that it contains three elements: processor unit, memory, and I/O(input/output). The borders between those three terms are highly ambigious,non-contiguous, and erratically shifting.
processors
Theprocessor is the part of the computer that actually does thecomputations. This is sometimes called an MPU (for main processor unit)or CPU (for central processing unit or central processor unit).
Aprocessor typically contains an arithmetic/logic unit (ALU), controlunit (including processor flags, flag register, or status register), internalbuses, and sometimes special function units (the most common special functionunit being a floating point unit for floating point arithmetic).
Somecomputers have more than one processor. This is called multi-processing.
Themajor kinds of digital processors are: CISC, RISC, DSP, and hybrid.
CISC
CISC stands for Complex Instruction SetComputer. Mainframe computers and minicomputers were CISC processors, withmanufacturers competing to offer the most useful instruction sets. Many of thefirst two generations of microprocessors were also CISC.
“Inmany computer applications, programs written in assembly language exhibit theshortest execution times. Assembly language programmers often know the computerarchitecture more intimately, and can write more efficient programs thancompilers can generate from high level language (HLL) code. The disadvantage ofthis method of increasing program performance is the diverging cost of computerhardware and software. On one hand, it is now possible to constrcut an entirecomputer on a single chip of semiconductor material, its cost being very smallcompared to the cost of a programmer’s time. On the other hand, assemblylanguage programming is perhaps the most time-consuming method of writingsoftware.
“Oneway to decrease software costs is to provide assembly language instructionsthat perform complex tasks similar to those existing in HLLs. These tasks, suchas the character selectinstruction, can be executed in one powerful assembly language instruction. Aresult of this philosophy is that computer instruction sets become relativelylarge, with many complex, special purpose, and often slow instructions. Anotherway to decrease software costs is to program in a HLL, and then let a compilertranslate the program into assembly language. This method does not alwaysproduce the most efficient code. It has been found that it is extremelydifficult to write an efficient optimizing compiler for a computer that has avery large instruction set.
“Howcan the HLL program execute more quickly? One approach is to narrow thesemantic distance between the HLL concepts and the underlying architectualconcepts. This closing of the semantic gap supports lower software costs, sincethe computer more closely matches the HLL, and is therefore easier to programin an HLL.
“Asinstruction sets become more complex, significant increases in performance andefficiency occurred.”
RISC
RISC stands for Reduced Instruction SetComputer. RISC came about as a result of academic research that showed that asmall well designed instruction set running compiled programs at high speedcould perform more computing work than a CISC running the same programs(although very expensive hand optimized assembly language favored CISC).
“Somedesigners began to question whether computers with complex instruction sets areas fast as they could be, having in mind the capabilities of the underlyingtechnology. A few designers hypothesized that increased performance should bepossible through a streamlined design, and instruction set simplicity. Thus,research efforts began in order to investigate how processing performance couldbe increased through simplified architectures. This is the root of the reducedinstruction set computer (RISC) design philosophy.
“SeymourCray has been credited with some of the very early RISC concepts. In an effortto design a very high speed vector processor (CDC 6600), a simple instructionset with pipelined execution was chosen. The CDC 6600 computer was registerbased, and all operations used data from registers local to the arithmeticunits. Cray realized that all operations must be simplified for maximalperformance. One complication or bottleneck in processing can cause all otheroperations to have degraded performance.
“Startingin the mid 1970s, the IBM 801 research team investigated the effect of a smallinstruction set and optimizing compiler design on computer performance. Theyperformed dynamic studies of the frequency of use of different instructions inactual application programs. In these studies, they found that approximately 20percent of the available instructions were used 80 percent of the time. Also,complexity of the control unit necessary to support rarely used instructions,slows the execution of all instructions. Thus, through careful study of programcharacteristics, one can specify a smaller instruction set consisting only ofinstructions which are used most of the time, and execute quickly.
“Thefirst major university RISC research project was at the University ofCalifornia, Berkeley (UCB), David Patterson, Carlos Séquin, and a group ofgraduate students investigated the effective use of VSLI in microprocessordesign. To fit a powerful processor on a single chip of silicon, they looked atways to simplify the processor design. Much of the circuitry of a moderncomputer CPU is dedicated to the decoding of instructions and to controllingtheir execution. Microprogrammed CISC computers typically dedicate over half oftheir circuitry to the control section. However, UCB researchers realized thata small instruction set requires a smaller area for control circuitry, and thearea saved could be used by other CPU functions to boost performance. Extensivestudies of application programs were performed to determine what kind ofinstructions are typically used, how often they execute, and what kind of CPUresources are needed to support them. These studies indicated that a largeregister set enhanced performance, and pointed to specific instruction classesthat should be optimized for better performance. The UCB research effortproduced two RISC designs that are widely referenced in the literature. Thesetwo processors developed at UCB can be referred to as UCB-RISC I and UCB-RISCII. The mnemonics RISC and CISC emerged at this time.
“Shortlyafter the UCB group began its work, researchers at Stanford University (SU),under the direction of John Hennessy, began looking into the relationshipbetween computers and compilers. Their research evolved into the design andimplementation of optimizing compilers, and single-cycle instruction sets.Since this research pointed to the need for single-cycle instruction sets,issues related to complex, deep pipelines were also investigated. This researchresulted in a RISC processor for VSLI that can be referred to as the SU-MIPS.
“Theresult of these initial investigations was the establishment of a designphilosophy for a new type of von Neumann architecture computer. Reducedinstruction set computer design resulted in computers that execute instructionsfaster than other computers built of the same technology. It was seen that astudy of the target application programs is vital in designing the instructionset and datapath. Also, it was made evident that all facets of a computerdesign must be considered together.
“Thedesign of reduced instruction set computers does not rely upon inclusion of aset of required features, but rather, is guided by a design philosophy. Sincethere is no strict definition of what constitutes a RISC design, a significantcontroversy exists in categorizing a computer as RISC or CISC.
“TheRISC philosophy can be stated as follows: The effective speed of a computer can be maximized by migrating all butthe most frequently used functions into software, thereby simplifying thehardware, and allowing it to be faster. Therefore, included in hardware areonly those performance features that are pointed to by dynamic studies of HLLprograms. The same philosophy applies to the instruction set design, as well asto the design of all other on-chip resources. Thus, a resource is incorporatedin the architecture only if its incorporation is justified by its frequency ofuse, as seen from the language studies, and if its incorporation does not slow downother resources that are more frequently used.
“Commonfeatures of this design philsophy can be observed in several examples of RISCdesign. The instruction set is based upon a load/store approach. Only load and store instructions access memory. No arithmetic, logic, or I/Oinstruction operates directly on memory contents. This is the key tosingle-cycle execution of instructions. Operations on register contents arealways faster than operations on memory contents (memory references usuallytake multiple cycles; however, references to cached or buffered operands may beas rapid as register references, if the desired operand is in the cache, andthe cache is on the CPU chip). Simple instructions and simple addressing modesare used. This simplificiation results in an instruction decoder that is small,fast, and relatively easy to design. It is easier to develop an optimizingcompiler for a small, simple instruction set than for a complex instructionset. With few addressing modes, it is easier to map instructions onto apipeline, since the pipeline can be designed to avoid a number of computationrelated conflicts. Little or no microcode is found in many RISC designs. Theabsence of microcode implies that there is no complex micro-CPU within the instructiondecode/control section of a CPU. Pipelining is used in all RISC designs toprovide simultaneous execution of multiple instructions. The depth of thepipeline (number of stages) depends upon how execution tasks are subdivided,and the time required for each stage to perform its operation. A carefullydesigned memory hierarchy is required for increased processing speed. Thishierarchy permits fetching of instructions and operands at a rate that is highenough to prevent pipeline stalls. A typical hierarchy includes high-speedregisters, cache, and/or buffers located on the CPU chip, and complex memorymanagement schemes to support off-chip cache and memory devices. Most RISCdesigns include an optimizing compiler as an integral part of the computer architecture.The compiler provides an interface between the HLL and the machine language.Optimizing compilers provide a mechanism to prevent or reduce the number ofpipeline faults by reorganizing code. The reorganization part of many compilersmoves code around to eliminate redundant or useless statements, and to presentinstructions to the pipeline in the most efficient order. All instructionstypically execute in the minimum possible number of CPU cycles. In some RISCdesigns, only load/store instructions require more than one cycle in which toexecute. If all instructions take the same amount of time, the pipeline can bedesigned to recover from faults more easily, and it is easier for the compilerto reorganize and optimize the instruction sequence.”
DSP
DSP stands for Digital SignalProcessing. DSP is used primarily in dedicated devices, such as MODEMs, digitalcameras, graphics cards, and other specialty devices.
Hybrid
Hybrid processors combine elements of twoor three of the major classes of processors.